• clock gating - 引用次数：23

  The clock gating technique is merely applicable to single edge-triggered flip-flop. It is a special kind of clock edge control technique.

  而门控时钟技术只适用于单边沿触发器,是一种特殊的时钟边沿控制技术。

  参考来源 - 时钟边沿控制技术及低功耗触发器研究
  gated clock - 引用次数：16

  The gated clock technique is discussed and used to instruct the microarchitecture partition.

  发展了门控时钟理论，讨论了门控时钟对系统划分的影响。

  参考来源 - 行为逻辑层上的SOC低功耗设计
  clock-gating - 引用次数：8

  This paper mainly discussed register clock-gating technique and resolved theproblems that would probably appeared such as design for testability (DFT) problemand timing problem. For RISC processer, clock-gating can reduce power by 18.8%.

  门控时钟技术是一种最常用的低功耗技术,本文着重研究了寄存器门控时钟技术,并对此技术中可能出现的可测性问题和时序问题进行了分析、解决;对于 RISC 微处理器,门控时钟技术可以降低功耗 18.8%。

  参考来源 - 数字集成电路低功耗设计技术的研究及应用
• clock gating - 引用次数：6

  Based on this, the clock management unit is introduced and the clock gating technique is employeed for the low power design of the processor core.

  在此基础上,本文引入了时钟管理单元并采用门控时钟技术降低功耗。

  参考来源 - 一种16位数字信号处理器内核的研究与设计
  gated clock - 引用次数：3

  Low-power processor most adopt the system-level design, the technologies include: reconfigurable dynamic cache and cache closed, gated clock technology, dynamic voltage scaling DVS technology, multi-core technology.

  处理器的低功耗设计大都采用系统级,其技术主要包括:可重配置的cache及动态关闭cache技术,门控时钟技术,动态电压缩放DVS(dynamic voltage scaling)技术,多核技术等。

  参考来源 - 嵌入式系统的低功耗研究

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