阐述了如何运用门控时钟来进行CMOS电路的低功耗设计。
This paper concentrates on using gated-clock in low-power design of CMOS circuits.
对于risc微处理器，门控时钟技术可以降低功耗18.8%。
此后，介绍了低功耗设计方法，本设计主要采用门控时钟结构来降低功耗。
Then the methods of low power design are introduced, and the clock gated is used in this design.
在幸存路径管理模块采用门控时钟的方法，有效地降低了对幸存路径存储部分的功耗。
SMU module adopts the clock-gating method was applied to the survivor path storage block, reduce the survivor path storage memory power dissipation effectively.
基于不同运算精度的门控时钟技术，在浮点单精度运算时彻底关闭空闲的低位数据以降低功耗。
When a single-precision operation was in process, the lower parts of data path which were idle will be shut down to save the unnecessary power dissipation.
这种综合流程在不改变原有电路设计的前提下同时采用了门控时钟、操作数隔离和门级功率优化来降低功耗。
This flow could use the gated clock, the operand isolation and the gate level optimization to decrease the power consumption without changing the original design.
同时介绍了该分频器各级门的动态特性以及内部用三态门控制结构的优点，给出了平均延迟时间的设计结果，该设计已应用于高频时钟芯片的大批量生产中。
The dynamic performance of the gates and the advantages of internal structure of tri-state gate control are also presented. Results of the averaged time delay design are given. which have bee...
同时介绍了该分频器各级门的动态特性以及内部用三态门控制结构的优点，给出了平均延迟时间的设计结果，该设计已应用于高频时钟芯片的大批量生产中。
The dynamic performance of the gates and the advantages of internal structure of tri-state gate control are also presented. Results of the averaged time delay design are given. which have bee...
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