时钟门控(Clock-Gating)一直以来都是降低微处理器功耗的重要手段,主要针对寄存器翻转带来的动态功耗。
Under the guide of the OSH-ASIP design method, a CI-dedicated low-power DSP is designed and implemented in 0.18μm CMOS process, with various low-power techniques including instruction-set reduction, wait mode, loop cache, memory partitioning, operand isolation and clock gating.
最后,在OSH-ASIP设计方法的指导下,综合运用指令集简化、等待模式、循环暂存、存储器切割、操作数隔离和时钟门控等多种低功耗设计技术,在0.18μm CMOS工艺下设计并实现了一款人工耳蜗专用的低功耗DSP。
参考来源 - 一种双模人工耳蜗系统及其低功耗数字信号处理器的设计·2,447,543篇论文数据,部分数据来源于NoteExpress
这种综合流程在不改变原有电路设计的前提下同时采用了门控时钟、操作数隔离和门级功率优化来降低功耗。
This flow could use the gated clock, the operand isolation and the gate level optimization to decrease the power consumption without changing the original design.
阐述了如何运用门控时钟来进行CMOS电路的低功耗设计。
This paper concentrates on using gated-clock in low-power design of CMOS circuits.
在幸存路径管理模块采用门控时钟的方法,有效地降低了对幸存路径存储部分的功耗。
SMU module adopts the clock-gating method was applied to the survivor path storage block, reduce the survivor path storage memory power dissipation effectively.
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