The second problem of test reuse is the design of SOC test architecture.
测试复用的第二个问题就是SOC测试结构设计问题。
First of all, several methods about testing technology and design for testability and SoC test techniques are summarized.
首先对测试技术和可测试性设计的一些方法做出了综述。
This paper introduces the special software and flow converted from VCD test vector to STIL test vector, which is based of SAPPHIRE SOC test System.
本文基于SAPPHIRE集成电路测试系统，介绍了自行开发的从VCD测试向量到STIL测试向量的转换软件及流程。
This technique solves some questions of test control in SOC design.
从而解决了SOC测试中控制部分的一些问题。
However SOC design also meets many challenges, test reuse is one of them.
但SOC设计也遇到诸多挑战，测试复用就是其中的挑战之一。
Experiments show that this testing frame can make an effective test on IP cores and take SOC environment of IP core into account while keeping high code coverage.
通过实验验证，该测试方法能够在保证一定代码覆盖率的前提下，对IP核进行有效的测试，并提高了测试后IP核的可移植性。
The paper proposed a new Selected Variable-length Input Coding (SVIC) for System on Chip (SOC) test data compression.
本文针对SOC测试数据压缩，提出了一种新的可挑选变长输入编码(SVIC)方案。
Recently, reducing test application time and test data volume is a direction of effort in SoC design .
目前，减少测试应用时间和测试数据容量是测试领域的努力方向。
Finally, a new test scheme to detect the crosstalk fault, based on the path delay inertia, for interconnection lines in SoC is proposed.
最后，我们提出一个利用路径延迟惯性原理，来测试系统电路连线之串音障碍的新测试方法。
A microprocessor based builtin test scheme for SOC is proposed, which employs transparency path test access mechanism.
提出了一种基于片上微处理器和透明路径测试访问的SO C自测试方案。
This paper presents the TAM optimization and test scheduling algorithm for multi-clock SOC, and it aims at decreasing test time of multi-clock SOC.
该文提出了用于多时钟域soc的TAM优化与测试调度算法，以减少多时钟域soc的测试时间。
Experimental results for two ITC '02 SOC benchmark show that the pair balance-based test scheduling achieves less test time compared to the previous approaches.
在ITC'02基准电路上的实验结果验证了基于对平衡测试调度算法的有效性。
A deterministic algorithm is proposed for System-on-Chip (SOC) test scheduling.
提出了一种确定性的片上系统(SOC)测试调度算法。
We test the hypothesis that sense of coherence (soc), a marker of social stress adaptive capacity, is associated with incident stroke in a population-based prospective cohort study.
在对基于种群的前瞻性队列研究中我们对一个相关性意义(SOC)的假说进行了试验，即对社会压力适应能力的标记与突发中风的相关性意义。
Therefore the research into the test bed of the rotation SOC, which can testify whether the clutch meets the standard technique, satisfies the market's increasingly demands.
研制旋转轴向式起动机单向离合器性能测试系统，能够在对其进行性能试验，检验其性能参数是否满足标准规定的技术条件，更好地满足日益提高的市场需求。
Test scheduling determines an assignment of cores to test access mechanism such that the overall test application time of system on chip (SOC) is minimized.
测试调度是系统芯片测试的一个重要方面，它用于确定把芯片上芯核的测试集分配给测试存取机制的方法，以使得总的测试时间最少。
The test control unit adopted SOC single chip C8051F040 processor which contained CAN controller to test and control its electric equipments.
测控单元均采用带CAN控制器的SOC单片机C8051F040处理器，测量和控制其电气设备。
Meanwhile the testing of SOC become more difficult and complex, Boundary-Scan-based Built-in-Test technology give a new solution.
与此同时，片上系统的测试问题也随之产生，基于边界扫描的内建自测试技术为片上系统的测试提供了新的解决方案。
Meanwhile the testing of SOC become more difficult and complex, Boundary-Scan-based Built-in-Test technology give a new solution.
与此同时，片上系统的测试问题也随之产生，基于边界扫描的内建自测试技术为片上系统的测试提供了新的解决方案。
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