In 2008, Trina is determined to "lower our module manufacturing costs through constant improvements in cell efficiencies, wafer thickness reduction, and manufacturing process innovation, " he added.

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Initial wafer runs on 32-nanometer process node suggest a quick ramp to high yields in 2010 and minimal additional development outlays.

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Bigger wafers mean more chips per wafer, and since a fair portion of the cost of a chip is in the process itself (the upfront development cost is another major piece), rather than the wafers, bigger wafers mean cheaper chips.

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