适用于飞利浦系列IIS总线芯片。
最后,在研究EP - H31580 1553总线芯片的基本功能和读写时序的基础上,完成了1553总线模块的硬件设计。
At last, 1553 bus circuit design has been finished on the basis of studying the basic function and timing of 1553 chip EP-H31580.
这是因为进程执行现在需要跨总线协调,以一半的芯片时钟频率进行处理。
This is because process execution now needs to be coordinated across the bus, which operates at half the clock frequency of the chip.
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