...I、SPI等; 高速外设模块:寄存器以SYSCLKOUT为时钟基准进行存取操作;SYSCLKOUT经高速分频器分频后,产生高速时钟(HSPCLK)。高速外设功能模块就以HSPCLK为时钟基准运行。
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缓存使用高速时钟频率下,缓存跟低比例的内存速度同样有用。
Use of caches At higher clock speeds, caches are useful as the memory speed is proportionally slower.
编号的,它反映了不同的特色,如光滑的雕刻,金额内存高速缓存,频率巴士的要求,或者时钟速度。
The numbered, it reflects various characteristics such as smoothness of engraving, the amount of memory cache, frequency of buses required, or clock speed.
由于反馈器件的限制,高速伪码不能采用单独依赖提高时钟频率的方法。
Because of the limits of feedback devices, high speed pseudo noise code generation cannot depend simply on the improvement of clock rate.
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