缓存使用高速时钟频率下，缓存跟低比例的内存速度同样有用。
Use of caches At higher clock speeds, caches are useful as the memory speed is proportionally slower.
编号的，它反映了不同的特色，如光滑的雕刻，金额内存高速缓存，频率巴士的要求，或者时钟速度。
The numbered, it reflects various characteristics such as smoothness of engraving, the amount of memory cache, frequency of buses required, or clock speed.
它内置一个低功耗、高速、16位不失码的采样adc、一个内部转换时钟和一个多功能串行接口。
It contains a low power, high speed, 16-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port.
由于反馈器件的限制，高速伪码不能采用单独依赖提高时钟频率的方法。
Because of the limits of feedback devices, high speed pseudo noise code generation cannot depend simply on the improvement of clock rate.
文章还对高速电路设计中电源层分配、时钟设计进行了讨论。
The power distribution system and the design of clock also included in this paper.
它内置一个16位高速采样adc、一个内部转换时钟、一个内部基准电压源(和缓冲)、纠错电路，以及串行和并行系统接口端口。
It contains a high speed 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports.
从综合的结果看该结构可在XC 4025e-2上以52mhz的时钟高速运行。在此基础上易于扩展为大点数fft运算结构。
The synthesis results show this FFT structure can run at 52mhz clock rate in XC4025E - 2. This FFT structure is easy to expand more points FFT structure.
本文还对高速电路设计中电源层分配、时钟设计进行了讨论。
The power distribution system and the design of clock are also included.
更高速率系统的研制目前也在开展中。时钟恢复电路(CRC)是光纤通信和许多类似数字通信领域中不可缺少的关键电路。
Clock recovery circuit (CRC) is the key component in the optical transmission systems as well as in the field of digital transmission.
该时钟板基于频率合成器来产生高精度、高稳定度、低抖动的时钟，用于高速高精度背板测试平台。
The system based on the frequency synthesizer can offer a high accuracy, high stability and low jitter clock for a high speed and high precision backplane test platform.
为了避免高速时序电路中常见的时钟偏差，在时钟树中放置了缓冲器。
In order to avoid clock skew familiar in high-speed sequential logic circuits, buffers are placed in clock-tree.
此外，为了避免高速时序电路中常见的时钟偏差，时钟通道采用负时钟偏差系统，并在时钟树中放置了缓冲器。
Furthermore, in order to avoid clock skew familiar in high-speed sequential logic circuits, negative clock skew system is used in clock routeway and buffers are placed in clock-tree.
该系统采用了片同步技术实现了采样后高速数字信号的可靠锁存，采用高精度的时钟管理芯片和设计合理的时钟路径对时钟抖动做了严格控制。
The Chip-Sync technology has been used to ensure the latch of high-speed signal, and we use high accuracy clock management chips and design reasonable clock way to strict control the clock jitter.
该器件内置一个高速18位采样ADC、一个内部转换时钟、一个内部基准电压缓冲、纠错电路，以及串行和并行系统接口。
The part contains a high-speed 18-bit samplingADC, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports.
针对这种情况，本文设计了一种基于DS80C 320高速单片机的GPS卫星同步时钟。
A kind of GPS satellite synchronous clock based on the DS80C320 High-speed SCM is recommended in the following thesis, to solve problem mentioned above.
它包括高速随机振荡信号发生器、交错停振控制单元、时钟发生器和采样单元。
The low power consumption digital true random source comprises a high speed random oscillator signal generator, an alternative oscillation stop control unit, a clock generator and a sampling unit.
在高速数据传输接口中，由于数据窗缩小以及传输路径不一致，造成数据和时钟信号在FPGA的接收端发生位偏移和字偏移。
Data may arrive at the FPGA receiver with channel -to -channel bit skew and word skew due to different trace length and smaller data window.
由于不匹配的电缆可引起过度的时钟相偏（Clock Skew），导致错误操作，所以相位匹配是有些高速数字电路中特别要注意的事项。
Phase matching is of particular concern with some high speed digital circuits, because unmatched cables may cause excessive clock skew, resulting in erroneous operation.
由于不匹配的电缆可引起过度的时钟相偏（Clock Skew），导致错误操作，所以相位匹配是有些高速数字电路中特别要注意的事项。
Phase matching is of particular concern with some high speed digital circuits, because unmatched cables may cause excessive clock skew, resulting in erroneous operation.
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