4．门级验证（Gate-Level Netlist Verification） 门级功能验证是寄放器传输级验证。首要的工作是要确认经综合后的电路是否合适功能需求，该工作一般操作门电路级验证对象完成。
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LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。
The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
随着设计规模的不断增加，芯片的平均设计门数已经超越百万级，验证已经成为设计流程中的主要瓶颈。
As the average gate count for designs now approaches or exceed on million, the verification has become the main bottleneck in design process.
改进了互补逻辑—交替互补逻辑(CL - ACL)结构，并做了考虑门级延迟的模拟验证。
Then, CL-ACL structure is improved, simulation and verification under real gate delay is done.
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