LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。
The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
随着设计规模的不断增加，芯片的平均设计门数已经超越百万级，验证已经成为设计流程中的主要瓶颈。
As the average gate count for designs now approaches or exceed on million, the verification has become the main bottleneck in design process.
改进了互补逻辑—交替互补逻辑(CL - ACL)结构，并做了考虑门级延迟的模拟验证。
Then, CL-ACL structure is improved, simulation and verification under real gate delay is done.
功能验证是百万门级IC设计中的一个重要瓶颈。
Functional verification is an important bottleneck in millions gates IC design.
本算法可直接结合到现有的RTL和门级网表的验证流程中，从而提高算术电路的验证能力。
The approach can be easily incorporated into existing RTL to gate equivalence checking frameworks and increase the robustness of equivalence checking for arithmetic circuits.
本课题结合项目的要求，对分组传送芯片组中一款千万门级的流量管理芯片进行了仿真验证。
Complying with the requirement of the project, the simulation of traffic managing chip with ten million gates in chips of packet transport networks is executed in this subject.
本文对于百万门级专用集成电路的成功实践，不仅是对FPGA验证理论的证实，而且从验证的思路和方法上对后续芯片有一定的指导意义。
The successfully completed of this multi-million gate ASIC, is not only the evidence to the FPGA verification theoretics, but also has a creative significance on other chip.
本文对于百万门级专用集成电路的成功实践，不仅是对FPGA验证理论的证实，而且从验证的思路和方法上对后续芯片有一定的指导意义。
The successfully completed of this multi-million gate ASIC, is not only the evidence to the FPGA verification theoretics, but also has a creative significance on other chip.
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