So, the test patterns generated according to fixed gate delay assignments may not activate faults, or weaken the difference between the average IDDT value of a fault-free circuit and a faulty circuit in real test applications.
因此，在实际测试应用中，根据固定门延时所产生的测试向量可能无法激活故障，也可能减小故障电路和无故障电路平均瞬态电流的差别而达不到可测的要求。
参考来源 - 基于非确定门延时的瞬态电流测试生成算法研究及BIST测试产生器设计·2,447,543篇论文数据，部分数据来源于NoteExpress
实践结果显示设计时间缩短、硬核性能得到提高，面积缩小48%，门延时缩短40%。
Experimental results with the less design time, area reductions of up to 48% and gate delay reduction of 40% demonstrate the effectiveness of the approach.
采用基于门延时的精细计数来量化被测时间间隔中与时钟不同步的部分，这样时间量就被转换成了数字量。
Both coarse count and fine count which base on the clock and gate delay separately were used to quantify them. Thus, time variable were converted into digital variable.
静态时序分析由于速度快和容量大而广泛应用于时序验证，而门延时的计算则是静态时序分析中的关键部分。
Static timing analysis is widely applied in timing verification because of its high speed and great capacity. The gate delay computing is a critical part of static timing analysis.
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