实践结果显示设计时间缩短、硬核性能得到提高，面积缩小48%，门延时缩短40%。
Experimental results with the less design time, area reductions of up to 48% and gate delay reduction of 40% demonstrate the effectiveness of the approach.
采用基于门延时的精细计数来量化被测时间间隔中与时钟不同步的部分，这样时间量就被转换成了数字量。
Both coarse count and fine count which base on the clock and gate delay separately were used to quantify them. Thus, time variable were converted into digital variable.
静态时序分析由于速度快和容量大而广泛应用于时序验证，而门延时的计算则是静态时序分析中的关键部分。
Static timing analysis is widely applied in timing verification because of its high speed and great capacity. The gate delay computing is a critical part of static timing analysis.
由于制造设备本身存在微小误差，具体门的延时并不相同，而是在一定范围内变化，引起波形变化的时间不确定。
Due to the subtle error among different manufacturing equipment, the gate delay of circuits is different and varies in a given scope, which induces the time uncertainty of the waveform.
首先，文章讨论了静态时序分析中的伪路径问题以及路径敏化算法，分析了影响逻辑门和互连线延时的因素。
Firstly, false paths in static timing analysis and the algorithm to sensitize paths are presented, and then some factors affecting gates and interconnects delay are discussed.
针对具有射击门体制的武器系统，研究其因加入射击门而产生的射击延时。
The shooting delay time as result of the equipped shooting gate is studied for the weapon system with shooting gate.
提出了使用延时芯片和ECL门产生极窄脉冲的方法，并对其产生原理做了理论分析。
This paper puts forward a method of using CMOS chip of delay and ECL gate to generate short pulse, and analyzes the principle of generation.
提出了使用延时芯片和ECL门产生极窄脉冲的方法，并对其产生原理做了理论分析。
This paper puts forward a method of using CMOS chip of delay and ECL gate to generate short pulse, and analyzes the principle of generation.
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