流水线 是 CPU 所使用的一个众所周知的概念，它用于减少取指令-译码-执行 周期中出现的延迟。
Pipelining is a well-known concept employed by CPUs for reducing the latency involved in the fetch-decode-execute cycle.
接收器一般由接收电路、放大电路、解调电路、指令译码电路、驱动电路和执行电路几部分组成。
Receiver general by the receiving circuit, amplifier, demodulator circuits, instruction decoder circuit, drive circuit and the implementation of the circuit composed of several parts.
按照指令译码的结果，这些指令的执行不会用到系统总线。
As with instruction decoding, the execution of these instructions does not make use of the system buses.
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