流水线是 CPU所使用的一个众所周知的概念，它用于减少取指令-译码-执行 周期中出现的延迟。
Pipelining is a well-known concept employed by CPUs for reducing the latency involved in the fetch-decode-execute cycle.
接收器一般由接收电路、放大电路、解调电路、指令译码电路、驱动电路和执行电路几部分组成。
Receiver general by the receiving circuit, amplifier, demodulator circuits, instruction decoder circuit, drive circuit and the implementation of the circuit composed of several parts.
按照指令译码的结果，这些指令的执行不会用到系统总线。
As with instruction decoding, the execution of these instructions does not make use of the system buses.
指令译码器将编码指令信号进行译码，最后由驱动电路来驱动执行电路实现各种指令的操作。
Encoding instruction decoder for decoding command signals, and finally by the drive circuit to drive the implementation of circuit operation to achieve a variety of commands.
控制部件从存储器中取出指令，并确定其类型或对之进行译码，然后将每条指令分解成一系列简单的、很小的步骤或动作。
The control unit fetches instructions from memory and determines their type or decodes them. It then breaks each instruction into a series of simple small steps or actions.
译码单元由指令缓存器和指令译码器构成，针对12位的指令代码翻译成16位控制信号，传送给处理器内部各个部件，用以保证各部件正常工作。
The encoding unit, composed of instruction buffer and command encoder, translates the 12-bit command code to 16-bit control signal, and ensures each part of the system to work steadily.
当微处理器对该指令译码时，它确定处理的是哪一条指令以便选择正确的操作序列去执行。
When the microprocessor decodes the instruction, it determines which instruction it is in order to select the correct sequence of operations to perform.
指令译码器集成丰富的指令集；
The instruction decoder integrates a large number of instructions.
指令译码器集成丰富的指令集；
The instruction decoder integrates a large number of instructions.
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