这种综合流程在不改变原有电路设计的前提下同时采用了门控时钟、操作数隔离和门级功率优化来降低功耗。

This flow could use the gated clock, the operand isolation and the gate level optimization to decrease the power consumption without changing the original design.

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时钟信号控制着数字系统的操作，它让逻辑门计算新的结果，然后由触发器存储执行结果。

Clock regulate the operation of a digital system by allowing time for new results to be calculated by logic gates and then capturing the results in flip-flops.

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采用基于门延时的精细计数来量化被测时间间隔中与时钟不同步的部分，这样时间量就被转换成了数字量。

Both coarse count and fine count which base on the clock and gate delay separately were used to quantify them. Thus, time variable were converted into digital variable.

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