对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。
The digital realization of monostable circuit and extraction of bit-synchronous signal with digital phase lock loop are also introduced in detail.
位同步检测是实现全数字接收机开环定时恢复的关键技术。
The bit synchronization detect is very important in opened loop timing recovery of all digital receivers.
HDL是设计数字逻辑电路必不可少的通用工具，该文给出了位同步性能较好的积分型自同步的一个HDL实现。
HDL is an essential general tool in digital logical circuit design. A HDL implementation of the integral bit synchronization with good performance is provided.
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