对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。
The digital realization of monostable circuit and extraction of bit-synchronous signal with digital phase lock loop are also introduced in detail.
位同步检测是实现全数字接收机开环定时恢复的关键技术。
The bit synchronization detect is very important in opened loop timing recovery of all digital receivers.
HDL是设计数字逻辑电路必不可少的通用工具，该文给出了位同步性能较好的积分型自同步的一个HDL实现。
HDL is an essential general tool in digital logical circuit design. A HDL implementation of the integral bit synchronization with good performance is provided.
码元定时恢复(位同步)技术是数字通信中的关键技术。
Symbol timing recovery (Bit Synchronization) is the key technology in the digital communication.
位同步时钟信号的提取是通信系统中的关键部分，应用数字锁相环可以准确地从输入码流中提取出位同步信号。
Bit synchronous clock recover circuit is the key part of the communication system, it can exactly recover the synchronous signal from input data stream.
本文根据突发式数字通信快速锁相要求，提出一种位同步信号提取的新的快速全数字锁相环方案。
This paper presents a new type of all digital phase-locked loop(ADPLL)used for extracting a bit-synchronous signal to meet the requirements of the fast phase-locked in burst digital communication.
针对传统超前-滞后型数字锁相环实现同步速度较慢的缺点，提出了一种基于步进和量化调整的数字锁相法的快速位同步方法。
Traditional Lag-Lead synchronous DPLL shortcomings slow. In order to solve this problem, proposed a method for FPGA-based realization method of fast bit synchronization.
针对传统超前-滞后型数字锁相环实现同步速度较慢的缺点，提出了一种基于步进和量化调整的数字锁相法的快速位同步方法。
Traditional Lag-Lead synchronous DPLL shortcomings slow. In order to solve this problem, proposed a method for FPGA-based realization method of fast bit synchronization.
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