可测试性设计 Design for Testing ; DFT ; design for test
关于可测试性设计 design-for-test ; DFT
可测试性设计及其前瞻 and Where It Goes
通过可测性设计，使该电路的测试难度及测试时间减少了将近一半。
By design for testability, both the degree of difficulty in testing and test time are reduced nearly one half.
从可测性设计角度讨论了信息安全处理芯片的芯片级测试控制器的设计以及相应核的可测性设计。
The design of chip test controller of a security chip and design for test of corresponding cores are discussed in detail.
系统级可测性设计主要是将存储器BIST与ARM核的边界扫描测试相结合。
SRAM BIST is also combined with ARM core's boundary scan testing during system level DFT.
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