vlsi layout verification vlsi版图验证
vlsi simulation verification vlsi模拟验证
formal VLSI correcthess verification 正规超大规模集成电路校正检验
The basic theory of resistance extraction in VLSI layout verification is described. A novel resistance extractor based on the boundary element method is presented.
介绍了VLSI版图验证中电阻提取的基本原理和主要方法，给出了一种新颖的基于边界元法的电阻提取算法。
Decision diagram model is a utility to represent data dependence between signals in VLSI designs, and is widely used in VLSI design verification.
决策图模型描述了VLSI设计信号间的数据依赖关系，在VLSI设计验证中有广泛的应用。
So the efficient verification of the design and implement of circuit must be introduced for building the higher responsible VLSI system.
为了设计和建立高可靠性的VLSI系统，必须对VLSI的设计和实现进行有效的验证。
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