The basic theory of resistance extraction in VLSI layout verification is described. A novel resistance extractor based on the boundary element method is presented.
介绍了VLSI版图验证中电阻提取的基本原理和主要方法，给出了一种新颖的基于边界元法的电阻提取算法。
Decision diagram model is a utility to represent data dependence between signals in VLSI designs, and is widely used in VLSI design verification.
决策图模型描述了VLSI设计信号间的数据依赖关系，在VLSI设计验证中有广泛的应用。
So the efficient verification of the design and implement of circuit must be introduced for building the higher responsible VLSI system.
为了设计和建立高可靠性的VLSI系统，必须对VLSI的设计和实现进行有效的验证。
This article has studied the function verification method which in the traditional VLSI design USES, has analyzed each method characteristic and the deficiency.
本文在研究了传统的VLSI设计中采用的功能验证方法后，分析了各种方法的特点和不足之处。
Refered to formal verification for VLSI, a new method to formally describe and verify assurance maintenance is brought forward.
引用数字硬件形式化证明的思想，提出了对保证维护进行形式化描述和验证的思路。
Refered to formal verification for VLSI, a new method to formally describe and verify assurance maintenance is brought forward.
引用数字硬件形式化证明的思想，提出了对保证维护进行形式化描述和验证的思路。
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