A static verification methodology for circuit design-flow of ASIC's based on very deep sub-micron CMOS technology is described in the paper.

介绍了基于深亚微米cmos工艺asic电路设计流程中的静态验证方法。

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A comparison of the static verification methodology with the dynamic verification methodology indicates that the former is more efficient and more accurate than the latter.

将这种验证方法与以往的动态验证方法进行了比较，结果表明，前者比后者更加高效和准确。

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Experimental results show that the proposed methodology can effectively improve the verification quality and increase the verification efficiency.

经由实验证明，我们所提议的方法的确可以有效的提高验证的品质，并且加快验证的效率。

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Though efforts continue to be made for greater emissions standardization, questions remain about the validity of many of the voluntary offsets that have been purchased and sold to date in the United States due to a lack of uniformity around methodology, monitoring, and verification.

FORBES: Should Companies Outsource Carbon Reduction?