A static verification methodology for circuit design-flow of ASIC's based on very deep sub-micron CMOS technology is described in the paper.
介绍了基于深亚微米cmos工艺asic电路设计流程中的静态验证方法。
A comparison of the static verification methodology with the dynamic verification methodology indicates that the former is more efficient and more accurate than the latter.
将这种验证方法与以往的动态验证方法进行了比较，结果表明，前者比后者更加高效和准确。
A comparison of the static verification methodology with the dynamic verification methodology indicates that the former is more efficient and more accurate than the latter.
将这种验证方法与以往的动态验证方法进行了比较，结果表明，前者比后者更加高效和准确。
应用推荐