With the establishing of verification and test platform for SDH chip, We realize the function simulation, timing simulation and performance test of the IP soft-core.

通过建立SDH芯片验证平台和SDH芯片测试平台，实现IP软核的功能仿真、时序仿真和芯片性能测试。

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The paper introduced the technology of IP Reuse, hardware and software co-design, SOC verification, measurement and low-power design on the SOC design.

介绍了SOC设计中的IP核可复用技术、软硬件协同设计技术、SOC验证技术、可测性设计技术以及低功耗设计技术。

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And finally, simulation results and verification by hardware test in FPGA show that the design of the IP core is valid and the proposed optimization strategy to reduce the memory is effective.

对以上优化设计方案进行了设计实现。仿真结果及FPGA硬件测试验证表明，文章提出的优化方案可行、有效，极大地降低了硬件资源占用和功耗。

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