For the test and verification of soft-IP, the paper presents a solution of Design For test technique, of which the BIST (Built-in Self test) is described in particular.
针对IP软核的测试、验证提出了面向测试、验证的IP软核设计方法—BIST内建自测试方法。
And finally, simulation results and verification by hardware test in FPGA show that the design of the IP core is valid and the proposed optimization strategy to reduce the memory is effective.
对以上优化设计方案进行了设计实现。仿真结果及FPGA硬件测试验证表明,文章提出的优化方案可行、有效,极大地降低了硬件资源占用和功耗。
The paper introduced the technology of IP Reuse, hardware and software co-design, SOC verification, measurement and low-power design on the SOC design.
介绍了SOC设计中的IP核可复用技术、软硬件协同设计技术、SOC验证技术、可测性设计技术以及低功耗设计技术。
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