gate level simulation 门电路级模拟 ; 逻辑闸层次模拟
gate level logic simulation [计] 门级逻辑模拟
simulation of asynchronous gate elements [计] [电子] 异步门元件模拟
conventional gate-level simulation [计] 传统的门级模拟
conventional gate level simulation 惯用闸位准模拟
gate-level logic simulation 门级逻辑模拟
The said digital gate circuit macro model can be used to perform a logical simulation for gate circurit and the digital circuit formed by the gate circuit.
提出了一种建立数字门电路宏模型的方法 ，采用该方法建立的门电路宏模型可以对门电路以及由门电路构成的数字电路进行逻辑仿真 。
We focus on the carrier synchronization method, the circuit and its parameters design, the performance simulation and the circuit implementation in Field Programmable Gate Array (FPGA).
重点研究载波同步方法，设计电路及参数，仿真同步性能，并在现场可编程门阵列(FPGA)上实现同步电路。
The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。
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