edge-sensitive scan design 边缘敏感扫描设计
level-sensitive scan design 电平敏感扫描设计
boundary scan design 边界扫描设计
full scan-design 全扫描设计
full scan design 全扫描设计
non-scan design for testability 非扫描可测性设计
non scan design for testability 非扫描可测性设计
LSSD Level Sensitive Scan Design 电平敏感扫描设计
Thus, only a very small extra chip area is required even if full scan design is used.
这样，即使采用全扫描设计，也仅需较小的芯片面积。
In This paper, based on analysis of the untested factors of the sequence cell, presents a design method, which the test logic inserted, before the scan design.
文中首先分析了时序元件的不可测因素，提出了扫描设计前增加测试逻辑的设计方法。
Full-scan design which upgrades the circuit in the controllability and observability greatly reduces the complexity of test generation, which is considered the most effective method of DFT.
全扫描设计通过提升电路的可控制性和可观察性，大大降低了测试生成的复杂度，被认为是最有效的可测性设计方法之一。
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