Full-scan design which upgrades the circuit in the controllability and observability greatly reduces the complexity of test generation, which is considered the most effective method of DFT.
全扫描设计通过提升电路的可控制性和可观察性，大大降低了测试生成的复杂度，被认为是最有效的可测性设计方法之一。
Thus, only a very small extra chip area is required even if full scan design is used.
这样，即使采用全扫描设计，也仅需较小的芯片面积。
Thus, only a very small extra chip area is required even if full scan design is used.
这样，即使采用全扫描设计，也仅需较小的芯片面积。
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