The most critical causes yielding the ISI as well as ICI are symbol timing and carrier frequency offset which are occurred in the OFDM receiver.
而产生ISI和ICI的主要原因是在OFDM系统接收端产生的符号定时偏差和载波频率偏差。
A frame synchronization detect circuit is designed based on the synchronization state machine using FPGA, and this circuit has functions of pre-protect, rear-protect and timing of the receiver.
采用FPGA设计了一种基于同步状态机的帧同步检测电路,具有帧同步的前方保护和后方保护以及接收端的定时功能。
All circuits are designed by HDL and can be intergrated in one CPLD or FPGA chip, used in the frame synchronization and timing of digital communications receiver.
全部电路由硬件描述语言实现,可以集成在一片CPLD或FPGA芯片内部,用于数字通信系统接收端的帧同步和定时。
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