... intercondenser 中间电容器；中间冷凝器 interconnect bus 中间联接总线 interconnect synchronization 互连同步 ...
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BIbus Backplane Interconnect Bus 底板互连总线
Element Interconnect Bus 总线 ; 执行单元内连总线 ; 连总线
Chip and module interconnect bus 片及模块间互连总线
Element Interconnect BUS Ring 单元互联总线环 ; 元互联总线环
media interconnect bus 媒体设备互连单元
peripheral interconnect bus 外部设备互连总线
Peripheral Component Interconnect Bus 外设部件互连总线
bus interconnect 总线互连
BI Bus Interconnect 总线互连
Each pod has its own processors and memory, and is connected to the larger system through a cache-coherent interconnect bus.
每个pod具有自己的处理器和内存，并通过一条高速缓存一致性互连总线(cache - coherent interconnect bus)连接到较大的系统。
The bus structure of the system: which devices connect to which bus and which buses are interconnected (for instance, a USB - PCI interconnect)?
系统的总线结构：哪个设备连接在哪个总线上，以及哪些总线互连(例如，USB和PCI总线的互连)？
This paper introduces the problems of Signal Integrity in high-speed parallel bus interconnect design and the new design methodology.
本文介绍了高速并行总线互连设计中出现的信号完整性问题及新的设计方法学。
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