BI Bus Interconnect 总线互连
Bus Interconnect Unit 总线接口单元
bus interconnect circuits 总线互连线电路
BIbus Backplane Interconnect Bus 底板互连总线
broadband optical bus interconnect network 宽带光总线互连网络
interconnect bus 中间联接总线
Element Interconnect Bus 总线 ; 执行单元内连总线 ; 连总线
Chip and module interconnect bus 片及模块间互连总线
Element Interconnect BUS Ring 单元互联总线环 ; 元互联总线环
Integrated circuit design has entered into the era of System on Chip (SoC), the bus interconnect architecture of System on Board have also developed into a kind of hierarchy architecture-On Chip Bus (OCB).
随着集成电路设计进入到系统芯片(SoC)时代，板极系统的总线互连结构也发展成为系统芯片的层次化总线体系一片上总线。
参考来源 - MLB/AHB总线桥的设计Based on the S7-300PLC marine electric cargo winch control system uses an advanced PROFIBUS technology,the frequency inverter,function modules,CPU,HMI(Human Machine Interface) TP270 together through a bus interconnect to achieve centralized control and management.
基于S7-300PLC的船用电动起货机控制系统采用了先进的现场总线PROFIBUS技术,把变频器、功能模块、CPU、人机界面TP270通过一根总线互连在一起,实现集中控制和管理。
参考来源 - 船舶起货机PLC复合控制的实现·2,447,543篇论文数据，部分数据来源于NoteExpress
This paper introduces the problems of Signal Integrity in high-speed parallel bus interconnect design and the new design methodology.
本文介绍了高速并行总线互连设计中出现的信号完整性问题及新的设计方法学。
The bus structure of the system: which devices connect to which bus and which buses are interconnected (for instance, a USB - PCI interconnect)?
系统的总线结构：哪个设备连接在哪个总线上，以及哪些总线互连(例如，USB和PCI总线的互连)？
Each pod has its own processors and memory, and is connected to the larger system through a cache-coherent interconnect bus.
每个pod具有自己的处理器和内存，并通过一条高速缓存一致性互连总线(cache - coherent interconnect bus)连接到较大的系统。
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