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instruction set
美 [ɪnˈstrʌkʃn set]

  • 指特定CPU可以执行的机器指令集合,对应的汇编语言助记符集合

网络释义专业释义英英释义

  指令集

指令集

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短语

instruction set [计] 指令集 ; 指令系统 ; 指令集合 ; 指令组

Complex instruction set computer 复杂指令集 ; 复杂指令集计算机 ; 复杂指令系统计算机 ; 复杂指令集电脑

Reduced instruction set computing 精简指令集 ; 精简指令系统计算机 ; 精简指令集计算 ; 精简指令集运算

Instruction Set Simulator 指令集仿真器 ; 指令集模拟器 ; 指令仿真器

instruction set architecture 指令集架构 ; 微处理器的指令集架构 ; 指令集结构

standard instruction set [计] 标准指令组

computer instruction set 计算机指令集 ; [计] 计算机指令系统 ; 计算机指令组

complete instruction set 完整指令集

commercial instruction set 商用指令集

 更多收起网络短语
  • 指令 - 引用次数:19

    Nowadays,more and more general-purpose microprocessors provide enhanced SIMD instruction-set extensions to exploit data level parallelism.

    SIMD指令能够高效开发数据级并行,因此当前绝大多数通用微处理器都支持这种机制。

    参考来源 - SIMD数据置换操作的自动生成和优化

·2,447,543篇论文数据,部分数据来源于NoteExpress

Instruction set

  • abstract: An instruction set, or instruction set architecture (ISA), is the part of the computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O. An ISA includes a specification of the set of opcodes (machine language), and the native commands implemented by a particular processor.

以上来源于: WordNet

双语例句权威例句

  • Because of the nature of memory systems and instruction-set designs, the best generic routine to copy memory is rarely as fast as code written to copy a particular length.

    由于内存系统和指令集设计的特性,用于复制内存的最佳通用例程的执行速度通常比用于复制特定长度的代码慢。

    youdao

  • To learn more about Parrot's instruction set, check out the opcodes available within it.

    要了解有关 Parrot 的指令集的更多内容,查看 其中可用的 opcodes。

    youdao

  • As with any instruction set, the Ant syntax is unable to express certain concepts.

    Ant的语法与其他所有的指令集相似,都不能表达某些特定的概念。

    youdao

更多双语例句
  • It is comprised of smaller revenue generating product lines such as digital light processing (DLP) projectors and reduced-instruction set computing (RISC) microprocessors.

    FORBES: Buying Tech: Texas Instruments

  • The Brahma15 is a 21, 000 DMIP Quad-core ARMv7-A instruction set compatible multiprocessor. 32KB instruction and 32KB data caches per processor are backed by a shared 2MB L2 cache and feed the multi-issue, out-of-order superscalar 15-stage plus write back pipeline of the Brahma15.

    ENGADGET: Broadcom's new ARM-based chip boosts Ultra HD TV into living rooms of the future

  • This time, however, Intel wants to crack the graphics market by doing the one thing it does best: cranking out chips able to run the so-called x86 instruction set that powers the overwhelming majority of modern computers.

    FORBES: Magazine Article

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