A low-power bitline architecture in SRAM was proposed, the low bitline voltage was realized by incorporating two techniques.

提出了一种用于SRAM的低功耗位线结构，通过两种途径来实现低位线电压。

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This allows efficient access to peripheral registers and flags located in SRAM memory without the need for a full Boolean processor.

这样就可以有效地对设备寄存器和位于SRAM中的某些标志位提供存取接口，而不再需要完整的布尔逻辑运算过程。

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In this thesis, the design and implementation of security strategies for data remanence in SRAM are comprehensively and thoroughly investigated.

本论文将全面深入地论述SRAM中数据残留的安全策略设计与实现。

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It minimizes the active power of the SRAM in certain conditions by monitoring the current consumption of the SRAM rest circuits.

ENGADGET: Toshiba mobile RAM uses prediction, adaptation to cut power use by up to 85 percent

This clearly points the way toward the first MRAM with the potential to surpass SRAM in practical operation.

ENGADGET: Toshiba goes perpendicular to solve MRAM's power issues, rethink cache memory

TOKYO--(BUSINESS WIRE)--Toshiba Corporation (TOKYO:6502) today announced the development of an innovative low-power technology for embedded SRAM for application in smart phones and other mobile products.

ENGADGET: Toshiba mobile RAM uses prediction, adaptation to cut power use by up to 85 percent