A low-power bitline architecture in SRAM was proposed, the low bitline voltage was realized by incorporating two techniques.
提出了一种用于SRAM的低功耗位线结构，通过两种途径来实现低位线电压。
This allows efficient access to peripheral registers and flags located in SRAM memory without the need for a full Boolean processor.
这样就可以有效地对设备寄存器和位于SRAM中的某些标志位提供存取接口，而不再需要完整的布尔逻辑运算过程。
In this thesis, the design and implementation of security strategies for data remanence in SRAM are comprehensively and thoroughly investigated.
本论文将全面深入地论述SRAM中数据残留的安全策略设计与实现。
After analyzing the producing mechanism of leakage power for each sub-circuit in SRAM, a leakage power model for each sub-circuit was established to estimate the leakage power for full SRAM.
在分析了SRAM逻辑结构中各子电路的泄漏功耗的产生机制的基础上，建立了SRAM的泄漏功耗模型，然后对SRAM的泄漏功耗进行估算。
FPGA is used to achieve the complex and high-speed logic control and the design of time sequence, with grabbed digital video signal cut and stored in SRAM, under the principles of the video signal.
利用FPGA完成复杂且高速的逻辑控制及时序设计，将采集的图像根据视频信号原理进行裁剪并存储在SRAM中。
SRAM is a common type of digital memory chip used in a wide variety of electronic systems for data storage.
SRAM是数字存储器片的通用类型，用在广泛的电子系统进行数据存储。
Using the equipment, successfully make SRAM radiation effect experiment in laser testing equipment of radiation effect and HI-13 tandem accelerator.
利用该装置在激光辐射效应实验装置及HI- 13串列加速器上成功地进行了SRAM的辐射效应实验。
A practical design of a dual-port SRAM embedded in OLED display driver ICs was presented.
详细描述了一种集成在OLED显示驱动芯片中的双端口SRAM设计。
The high-speed and low power SRAM has become a hot research area in today's digital research fields.
目前，高速低功耗SRAM的研究成为数字集成电路领域中的研究热点之一。
The paper introduces a method of simulating dual-port RAM with SRAM by TDMA in the data collecting system composed of an m 51 microprocessor.
介绍了一种在51单片机采集系统中，使用普通SRAM，采用时分复用模似双口ram的方法。
Claimed weights range from 755-780 grams, which includes bottom bracket and puts them firmly in the ballpark of SRAM XX despite the aluminum arms.
声称重量范围从755-780克，其中包括中轴和放入的SRAM二十球场他们牢固尽管铝武器。
Designers traditionally think of SRAM in its most basic form, a single-ported, single-clock domain device.
设计人员总把SRAM作为其最基本的形式，即单端口、单时钟域器件。
In this example, the metal one layer of a SRAM cell has been modified to reduce the probability of shorts between metal one nodes.
在这个例子中，静态随机存储器单元的金属层已被修改，以降低金属节点之间短路的概率。
A 32kb Static Random Access Memory (SRAM), which is widely used at present in VLSI, is designed in this paper.
目前，片上集成存储器一般采用静态结构，本文设计了一款32KB容量的静态随机存储器(SRAM)。
This paper introduced a soft built-in self-repair mechanism for embedded SRAM, and analyzed repair efficiency and area overhead of this mechanism.
本文介绍一种分段列冗余的软修复机制，并分析该修复机制的性能、面积开销。
This paper presents a hardware structure-independent weight-based fault injection model for accurate emulation of the radioresistance in the SRAM-based FPGA.
提出一种与具体硬件结构无关、基于权重的错误注入模型，用于准确模拟基于SRAM的现场可编程门阵列抗辐射性能。
In this system, two single chip computers communicate with each other through dual port SRAM to realize high speed picture and work for display scan and graphic process respectively.
该系统采用两片单片机分别负责显示扫描和图形变换，两者通过双口sram连接，实现高速图形显示。
Decoder is one of the most important components in a memory unit, and its improvement can greatly diminish the access time of both register file and SRAM.
译码器是存储部件关键路径的重要组成部分，提高译码速度能有效提高寄存器文件和SRAM的读写速度。
We apply both two methods in the design of SRAM decoder and achieve a satisfying result.
SRAM的译码使用这两种技术，取得了很好的效果。
To provide the energy to accomplish secure operations in powered-off SRAM, a fully integrated power supply system to realize the on-chip acquisition, storage, and conversion of energy is proposed.
提出了一种能实现片上能量获取、存储、转换的全集成电源系统，为掉电后的SRAM提供进行安全操作所需的能量。
In practical applications, the security of SRAM and its applied system has been greatly threatened by it.
在实际应用中，这给SRAM及其系统的安全性构成一定威胁。
As it has the characteristic of high operation speed and low power consumption, SRAM is widely used in many high performance microprocessor and various consumer electronic products.
由于其高速、低功耗的特点，SRAM被广泛地应用于高性能微处理器和各类消费电子产品中。
IBM-alliance researchers optimized the SRAM cell design and circuit layout to improve stability and developed several novel fabrication processes in order to make the new SRAM cell possible.
IBM联盟的研究人员优化了SRAM单元的设计和电路图，从而提升了稳定性，此外，为了制造新型SRAM单元，他们还开发出几种新的制作工艺流程。
In one embodiment, the semiconductor device includes a static random access memory (SRAM) cell having numerous NFETs (110) and PFETs (112).
在一个实施例中，所述半导体器件包括具有多个NFET(110)和多个PFET(112)的静态随机存取存储器(SRAM)单元。
The system makes use of two group of outer SRAM to buffer the frame data, and USES ping-pong operation of the SRAM to achieve the video display in series.
系统利用两组外部SRAM对帧数据进行缓存，采用乒乓操作来实现视频的实时连续显示。
As a class of most important cache for the embedded IP application, Static Random Access Memory (SRAM) has become one of the hottest research topics in the digital integrated circuits field.
静态随机存储器SRAM作为嵌入式IP应用的一类最主要的高速缓存，已经成为当前数字集成电路领域的一大研究热点。
As a class of most important cache for the embedded IP application, Static Random Access Memory (SRAM) has become one of the hottest research topics in the digital integrated circuits field.
静态随机存储器SRAM作为嵌入式IP应用的一类最主要的高速缓存，已经成为当前数字集成电路领域的一大研究热点。
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