gate level simulation 门电路级模拟 ; 逻辑闸层次模拟
conventional gate-level simulation [计] 传统的门级模拟
conventional gate level simulation 惯用闸位准模拟
gate level logic simulation [计] 门级逻辑模拟
gate-level logic simulation 门级逻辑模拟
The netlist of synthesis has passed the gate-level simulation.
最后，对逻辑综合产生的门级网表进行了门级仿真。
参考来源 - 8位MCU IP核的设计与应用·2,447,543篇论文数据，部分数据来源于NoteExpress
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