gate level simulation 门电路级模拟 ; 逻辑闸层次模拟
conventional gate-level simulation [计] 传统的门级模拟
conventional gate level simulation 惯用闸位准模拟
gate level logic simulation [计] 门级逻辑模拟
gate-level logic simulation 门级逻辑模拟
The netlist of synthesis has passed the gate-level simulation.
最后，对逻辑综合产生的门级网表进行了门级仿真。
参考来源 - 8位MCU IP核的设计与应用·2,447,543篇论文数据，部分数据来源于NoteExpress
A new analytical model and some algorithms based on the conventional gate-level simulation are presented in this article.
本文在传统的门级逻辑模拟模型和算法的基础上引进了一些新概念，导出了一种新的分析模型和算法。
The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。
The design of MCS-51 Microcontroller is followed the Top-Down design way, including system partition coding (VHDL) RTL simulation synthesis, gate level simulation ect.
对MCS—51单片机进行正向设计，包括系统划分、编写代码、RTL级仿真与综合、门级仿真等。
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