floating point adder 浮点加法器 ; 浮点数加法器
floating-point adder [计] 浮点加法器
3-input floating-point adder 输入浮点加法器
The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。
The main research area is the structure optimization of floating-point adder, which is intent to minimize the delay of floating-point addition and optimize the circuit structure.
主要研究方向是优化浮点加法器结构，减小浮点加法运算的延迟，优化电路结构。
The main research area is the structure optimization of floating-point adder , which is intent to minimize the delay of floating-point addition and optimize the circuit structure.
主要研究方向是优化浮点加法器结构，减小浮点加法运算的延迟，优化电路结构。
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