floating point adder 浮点加法器 ; 浮点数加法器
Then the description of the design of the hardware architecture of the floating-point multiplier and the floating-point adder is made, in which several novel techniques are adopted such as high-speed fixing-point multiplier, fast leading-0-detector-logic and pipeline etc.
随后,论文介绍了浮点乘法器和浮点加减法器的硬件结构设计。 其中采用了高速定点乘法器、快速前导零检测逻辑等几种新技术,并使用了流水线设计思想。
参考来源 - 基于FPGA的高性能32位浮点FFT IP核的开发·2,447,543篇论文数据，部分数据来源于NoteExpress
Through the structure and logical designing, we get a high-speed and effective LOD circuit, which applied in floating-point adder.
我们从LOD的组成结构和逻辑两个方面进行设计，实现了一种快速、高效的LOD电路。
The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。
The main research area is the structure optimization of floating-point adder, which is intent to minimize the delay of floating-point addition and optimize the circuit structure.
主要研究方向是优化浮点加法器结构，减小浮点加法运算的延迟，优化电路结构。
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