Digital ASIC front-end design and verification methods is used in digital logic part design.

数字逻辑部分的设计采用数字asic的前端设计及验证方法。

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The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.

LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。

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It is proved that this type of counter has correct logic function according to EDA simulation and experimental verification with FPGA and can be normally used in the design of digital system.

经eda软件模拟仿真和FPGA硬件验证，表明该计数器具有正确的逻辑功能，能够正常地应用于数字系统的设计。

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