With the development of integrated circuit design goes into nanometer era, the progress of process brings new challenges to the design of embedded SRAM.
随着集成电路设计进入纳米时代,工艺的进步对嵌入式SRAM的设计提出了新的挑战。
参考来源 - 嵌入式CPU的纳米尺度SRAM设计研究That isolation logic and power on/off states are added to reduce power consumption in test mode, an optimization method of embedded SRAM for low power, is proposed in this thesis.
本文提出了一种嵌入式SRAM的低功耗优化方法:增加隔离逻辑及电源开启/关闭状态以降低测试模式下的功耗。
参考来源 - 嵌入式SRAM的优化设计方法与测试技术研究·2,447,543篇论文数据，部分数据来源于NoteExpress
This paper introduced a soft built-in self-repair mechanism for embedded SRAM, and analyzed repair efficiency and area overhead of this mechanism.
本文介绍一种分段列冗余的软修复机制，并分析该修复机制的性能、面积开销。
With the continuously improving of the microelectronics craft technique level, embedded SRAM present a trend of the higher integration, higher speeding and lower power.
随着微电子工艺技术水平的不断提高，嵌入式SRAM呈现出更高集成度、更快速及更低功耗的发展趋势。
As a class of most important cache for the embedded IP application, Static Random Access Memory (SRAM) has become one of the hottest research topics in the digital integrated circuits field.
静态随机存储器SRAM作为嵌入式IP应用的一类最主要的高速缓存，已经成为当前数字集成电路领域的一大研究热点。
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