An efficient network comparison algorithm for layout verification of integrated circuits is presented.
提出了一种有效的验证集成电路版图的网络比较算法。
It is a sequence comparison algorithm optimized for speed used to search sequence databases for optimal local alignments to a query.
它是一个最佳化的序列比对演算法：为了能让在搜寻序列资料库的速度加快，而做了个别电脑上比对要求的最佳化。
The paper also gives the achievement of text comparison algorithm based on sentence similarity on the computer. And then validate it with some relevant texts.
文中也给出了关于句子相似度的文本比对算法的计算机实现过程，并利用相关文本进行了测试，对所用的方法进行验证。
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