A new hierarchical approach for layout circuit extraction was presented to increase its efficiency.

为提高版图电路提取效率，提出了一种新的层次式版图电路提取方法。

youdao

VLSI layout circuit extraction provides a reliable tool for the estimation of circuit's performance.

集成电路版图提取为精确估计电路性能提供了可靠的手段。

youdao

The digital realization of monostable circuit and extraction of bit-synchronous signal with digital phase lock loop are also introduced in detail.

对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。

youdao

The multi-year collaboration delivered the foundational modeling technologies for 3D parasitic extraction, circuit simulation and physical design-rule support of FinFET devices.

ENGADGET: Samsung reveals its first 14nm FinFET test chip, should offer substantial power improvements in future silicon