...锁存器法,结绳法,异步FIFO,异步比较. [gap=316]Keywords: asynchronous timing, MTBF,two registers, toggle, asynchronous FIFO, asynchronous ...
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bidirectional asynchronous FIFO 双向异步FIFO
High speed asynchronous FIFO 高速异步FIFO
asynchronous receive fifo 异步接收先入先出
Asynchronous FIFO is a general way to communicate between different clock domains.
异步FIFO是一种不同时钟域之间传递数据的常用方法。
参考来源 - 期刊学术社区This article introduces a design of high speed data transmission between FPGA and DSP based on asynchronous FIFO which is used in spectrum analysis,and illuminate it’s implementation in FPGA.
本文介绍了一种利用异步FIFO实现的应用于频谱分析的FPGA与DSP之间的高速数据传输设计,并介绍了这种设计在FPGA内的实现。
参考来源 - 一种灵活高速的数据传输设计及其在FPGA中的实现·2,447,543篇论文数据，部分数据来源于NoteExpress
Asynchronous FIFO is a general way to communicate between different clock domains.
异步fifo是一种不同时钟域之间传递数据的常用方法。
Metastability and how to generate empty and full flag correctly is key in the design of asynchronous FIFO.
避免亚稳态问题及空满控制信号的产生是异步fifo设计的两个关键。
The design of asynchronous FIFO meets with two troubles, metastability and how to generate empty and full flag correctly.
避免亚稳态问题及空满控制信号的产生是异步fifo设计的两个难题。
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