Asynchronous FIFO is a general way to communicate between different clock domains.

异步fifo是一种不同时钟域之间传递数据的常用方法。

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Metastability and how to generate empty and full flag correctly is key in the design of asynchronous FIFO.

避免亚稳态问题及空满控制信号的产生是异步fifo设计的两个关键。

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The design of asynchronous FIFO meets with two troubles, metastability and how to generate empty and full flag correctly.

避免亚稳态问题及空满控制信号的产生是异步fifo设计的两个难题。

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In this article, we introduce the ping pong operation into the asynchronous FIFO design and provide a FIFO design scheme in FPGA.

根据异步fifo的设计方法，引入乒乓操作的设计技巧，给出了一种用FPGA实现异步fifo的设计方案。

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In this article, we introduce the ping pong operation into the asynchronous FIFO design and provide a FIFO design scheme in FPGA.

根据异步fifo的设计方法，引入乒乓操作的设计技巧，给出了一种用FPGA实现异步fifo的设计方案。

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