所有现代的CPU必须使用本地存储的缓存，将获取指令和数据的延迟降到最低。

All modern CPUs must utilize local memory cache to minimize latency of fetching instructions and data from memory.

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由此造成的上下文切换相对于锁保护的少数几条指令来说，会造成相当大的延迟。

The resulting context switches can cause a significant delay relative to the few instructions protected by the lock.

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流水线 是 CPU 所使用的一个众所周知的概念，它用于减少取指令-译码-执行 周期中出现的延迟。

Pipelining is a well-known concept employed by CPUs for reducing the latency involved in the fetch-decode-execute cycle.

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