所有现代的CPU必须使用本地存储的缓存，将获取指令和数据的延迟降到最低。
All modern CPUs must utilize local memory cache to minimize latency of fetching instructions and data from memory.
由此造成的上下文切换相对于锁保护的少数几条指令来说，会造成相当大的延迟。
The resulting context switches can cause a significant delay relative to the few instructions protected by the lock.
在获取每条指令期间会出现某种延迟，可以通过预取指令并对其进行存储以用于后续的执行，从而避免延迟。
Fetching each instruction involves a certain latency that can be avoided by prefetching instructions and storing them for later execution.
流水线是 CPU所使用的一个众所周知的概念，它用于减少取指令-译码-执行 周期中出现的延迟。
Pipelining is a well-known concept employed by CPUs for reducing the latency involved in the fetch-decode-execute cycle.
在理想情况下，输出能无延迟、无超调地跟踪输入指令的变化。
In the ideal case, the output is able to track the changes of the input command without delay and overshoot.
总的来说，指令集中的指令数越多，CPU中的传播延迟越大。
In general, the greater the number of instructions set, the larger the propagation delay is within the CPU.
通信延迟包括遥控指令的延迟和遥测信号的延迟，主要是由光传播速度造成的。
The communication time-delay concludes the delay of remote control commands and telemetry signals, which is brought by light transportation speed.
通信延迟包括遥控指令的延迟和遥测信号的延迟，主要是由光传播速度造成的。
The communication time-delay concludes the delay of remote control commands and telemetry signals, which is brought by light transportation speed.
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