缺陷是影响集成电路成品率与可靠性的主要因素。
The defect is a main factor of affecting IC's yield and reliability.
本文提出了一种基于数值积分的集成电路成品率估计方法。
A novel integration-based yield estimation method is developed for yield optimization of integrated circuits.
对集成电路成品率的损失机理作了详细论述。最后，详细介绍了功能成品率的分析模型。
Mechanisms of the IC functional yield loss are discussed in particular and the analysis model of the IC functional yield is introduced in detail.
版图图像转移过程的失真，将影响产品的性能参数，直接降低了集成电路的成品率。
The distortion in pattern transferring process may influence functionality and performance of IC products and lower the production yield.
本文介绍了一种新颖的集成电路分档成品率的优化模型及求解。
A novel optimal model and its solving to the layer yield of IC's is presented.
这种成品率模型可以扩充到包含更复杂的备用电路系统的芯片。
This yield model can be extended to chips containing more complex redundant circuitry.
光刻是大规模集成电路生产流程中十分关键的一环，而光刻中使用的掩模的质量对大规模集成电路的成品率有很大的影响。
In the manufacture process of integrated circuit (IC), lithography occupy a very important step, and the quality of photomask used in lithography affects the yield of LSI.
利用关键面积的思想分析了冗余电路的成品率，并给出了其计算模型。
Yield of the redundant circuit is analyzed with IC critical area and the computational model of this redundant circuit is given.
集成电路参数成品率的研究是集成电路可制造性工程和设计研究的重要内容之一。
The integrated circuits parametric yield is important problem of the IC designing and manufacture engineering.
算例表明，该方法对电路设计进行快速成品率分析及电路的稳定性设计具有较好的应用前景。
Experience example demonstrates that the proposed method is very useful in yield analysis of electronic circuit design.
为了实现微波电路的高成品率和良好性能，在设计阶段就必须要对不连续性问题进行准确建模和研究。
In order to realize high-performance microwave circuits, it is necessary to establish accurate models and to analyze for these discontinuities.
电子电路的统计分析在电子产品批量生产前对产品元器件容差的选取、产品成品率和生产成本预测上有很好的指导意义。
Statistic analysis of electronic circuit has a practical guidance significance on tolerance selection of electronic components, forecast of qualified products ratio and costs of production.
冗余物缺陷是影响IC晶片成品率下降的重要原因，主要造成电路短路错误。
The redundancy material defect is an important factor of reducing the yield of IC, it mainly causes circuits to be connection failure.
随着芯片面积的增加及电路复杂性的增强，芯片的成品率逐渐下降，为了保证合理的成品率，人们将容错技术结合入了集成电路。
An increase in chip area and circuit complexity leads to a reduction in the yield of chip production. In order to get a fair yield, the fault tolerant technique is introduced into the IC design.
超大规模集成电路(VLSI)中的参数成品率最优化问题一直是集成电路可制造性设计的重点研究问题。
The maximum problem of parametric yield in VLSI is always an important issue in design for manufacturing (DFM).
超大规模集成电路(VLSI)中的参数成品率最优化问题一直是集成电路可制造性设计的重点研究问题。
The maximum problem of parametric yield in VLSI is always an important issue in design for manufacturing (DFM).
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