在一个数据锁存如果LE是低，时钟是在高或低的逻辑电平举行。
The a data is latched if le is low and clock is held at a high or low logic level.
译码电路接收测量端模拟信号，转化为7段显示的数字信号，发送到数据锁存器上。
The A/D decoding circuit received simulation signal form measurement port and converted the signals into data signals which displayed by 7-segment, then signals were sent to data latch.
每个器件都有一个八位CMOS移位寄存器和CMOS控制电路，八个CMOS数据锁存，八个双极电流吸收达林顿输出驱动器。
Each device has an eight-bit CMOS shift register and CMOS control circuitry, eight CMOS data latches, and eight bipolar current-sinking Darlington output drivers.
发生这一问题的原因在于数据库内的索引锁定或锁存(例如事务处理日志周围的索引锁定或锁存)，直到该应用程序使用分区数据库为止。
This happens because the index locks or latches within the database (such as those surrounding the transaction log) until the application is using a partitioned database.
为了得知外设是否就绪，CPU必须不停地轮询接口(读状态寄存器)并最终锁存数据。
In order to know this, the CPU must be continually 'polling' the interface (reading the status register), and finally latched the data.
一种用于确定存储在PROM中数据的完整性的方法和设备，其中PROM配置了至少一个连接到两组块的保持锁存器。
A method and apparatus for determining the integrity of data stored in a PROM device provides at least one holding latch connected to two sets of blocks.
利用乒乓锁存降低了对缓存速度的要求并将数据合并成32位，易于与DSP数据传输。
The buffer velocity is fell by using PingPong latch which combine data into 32 bits being easy to connect with DSP.
同时，为了解决高速数据存储的失误问题，提出了二次锁存方案。
To solve the problem of storing data falsely, a scheme of a double pulse-latching scheme is presented.
所述动态锁存器适于至少部分基于输入数据信号产生放大的输出数据信号。
The dynamic latch is adapted to generate an amplified output data signal based at least in part on the input data signal.
所述动态锁存器包括至少一个耦合在所述至少一个输入端子和所述至少一个锁存器端子之间的电容器，以减少所述输入数据信号中的码间干扰。
The dynamic latch includes at least one capacitor, coupled between the at least one input terminal and the at least one latch terminal, to reduce intersymbol interference in the input data signal.
在一些实施例中，接收机锁存器电路包括动态锁存器，该动态锁存器具有至少一个用于接收输入数据信号的输入端子和至少一个锁存器端子。
In some embodiments, a receiver latch circuit, includes a dynamic latch having at least one input terminal to receive an input data signal and at least one latch terminal.
锁存电路可被配置为锁存在输出节点处生成的输出数据信号。
The latch circuit may be configured to latch an output data signal generated at the output node.
锁存电路可被配置为锁存在输出节点处生成的输出数据信号。
The latch circuit may be configured to latch an output data signal generated at the output node.
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