在一个数据锁存如果LE是低，时钟是在高或低的逻辑电平举行。

The a data is latched if le is low and clock is held at a high or low logic level.

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译码电路接收测量端模拟信号，转化为7段显示的数字信号，发送到数据锁存器上。

The A/D decoding circuit received simulation signal form measurement port and converted the signals into data signals which displayed by 7-segment, then signals were sent to data latch.

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每个器件都有一个八位CMOS移位寄存器和CMOS控制电路，八个CMOS数据锁存，八个双极电流吸收达林顿输出驱动器。

Each device has an eight-bit CMOS shift register and CMOS control circuitry, eight CMOS data latches, and eight bipolar current-sinking Darlington output drivers.

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