Bochs的内部指令缓存为传统JIT编译进行了很好的权衡。
Bochs's internal instruction cache provides a nice trade-off to traditional JIT compilation.
更有用的两个优化是更好的内联支持和利用指令缓存局部性的能力。
Two of the more useful optimizations are better inline support and the ability to exploit the instruction cache locality.
I -cache失效(处理器无法从指令缓存获取下一个指令)。
I-cache miss (Processor cannot get the next instruction from instruction cache).
在现代处理器上由于广泛使用指令缓存，小代码通常会运行得更快。
On modern processors smaller code usually runs faster due to better use of the instruction cache.
与将冷函数填入缓存相比，将热函数(也就是那些更常用的函数)放在一起可以更好地利用指令缓存。
Keeping hot functions together (that is, those functions that are used more often) results in better instruction cache use compared to polluting the cache with cold functions.
它还通过存储原始x86系统的“微操作”来维护指令缓存(其后可在没有解码开销的情况下提取)，进而改进性能。
It also maintains an instruction cache for improved performance by storing the "micro operations" of the original x86 system (which can be fetched later without the overhead of decoding).
译码单元由指令缓存器和指令译码器构成，针对12位的指令代码翻译成16位控制信号，传送给处理器内部各个部件，用以保证各部件正常工作。
The encoding unit, composed of instruction buffer and command encoder, translates the 12-bit command code to 16-bit control signal, and ensures each part of the system to work steadily.
这些指令指定用于阻止缓存对请求或响应造成不利干扰的行为。
The directives specify behaviors intended to prevent caches from adversely interfering with the request or response.
它还可以改进缓存和指令流水线。
这个字段用于指定所有缓存机制在整个请求/响应链中必须服从的指令。
This field is used to specify directives that must be obeyed by all caching mechanisms along the request/response chain.
在某些情况下，服务器或客户机可能需要为HTTP缓存提供显式指令。
In some cases, a server or client might need to provide explicit directives to the HTTP caches.
内联汇编有时也是必须的，举例来说，当您需要确保特定指令集都在相同的缓存线上(否则就会浪费内存映像)时。
Inline assembly is also sometimes needed when you have to, for instance, ensure that a particular set of instructions are in the same cache line, or otherwise mess around with memory maps.
所有现代的CPU必须使用本地存储的缓存，将获取指令和数据的延迟降到最低。
All modern CPUs must utilize local memory cache to minimize latency of fetching instructions and data from memory.
PPE用载入和存储指令访问主存储器(有效地址空间)，可以在主存储器与内容可以缓存的私有寄存器文件之间移动数据。
The PPE accesses main storage (the effective-address space) with load and store instructions that move data between main storage and a private register file, the contents of which may be cached.
这些指令通常覆盖默认缓存算法。
These directives typically override the default caching algorithms.
这使它与缓存操作非常类似，后者是将指令块从内存移动到本地快速缓存中执行。
This makes it very similar to caching operations, where blocks of instructions are moved from memory into a local fast cache memory for execution.
在下一个对话框中，配置哪些内存空间可缓存指令和数据。
In the next dialog, you can configure which memory Spaces will be cacheable for instructions and data.
这既不需要使用内存管理单元，也不需要使用指令或数据缓存。
Neither a memory management unit nor an instruction or data cache are used.
proxy -revalidate指令是一个变体，它要求对公共缓存进行验证。
A variant, the proxy-revalidate directive, requires public caches to validate.
指令must -revalidate强制所有缓存都验证响应。
The directive must-revalidate forces all caches to validate responses.
默认情况下，varnishd既不缓存带有cookie的响应，也不遵守cache - Control指令private和no - cache。
Out of the box, varnishd does not cache a response with a cookie, nor does it honor the Cache-Control directives private and no-cache.
如果数据或指令没有出现在高速缓存中，或者如果高速缓存线路无效的时候，CPU通过从主存储器中读数据来更新它的高速缓存。
If the data or instruction is not present in the cache, or if the cache line is invalidated, the CPU updates its cache by reading the data from the main memory.
此指令配置页面以进行缓存。
在基于冯诺依曼架构的计算机中（没有CPU缓存），CPU或者从存储器中读取指令或数据，或者在存储器中写入数据。
In a computer with the contrasting von Neumann architecture (and no CPU cache), the CPU can be either reading an instruction or reading/writing data fROM/to the memory.
指令设置了类型和存储SSL会话的缓存的大小。
The directive sets the types and sizes of caches to store the SSL sessions.
在任何情况下指令存储器所对应的地址空间都是可缓存的。
The address space corresponding to instruction memory is always indicated cacheable, which is correct in function.
本指令指定LDBM后台数据库实例维护的内存缓存中条目数。
This directive specifies the size in entries of the in-memory cache maintained by the LDBM backend database instance.
在使用哈佛架构的计算机中，即使没有缓存，CPU也可以在读取指令的同时进行数据访问。
In a computer using the Harvard architecture, the CPU can both read an instruction and perform a data memory access at the same time, even without a cache.
本文提出面向访问需求的数据缓存泄漏功耗管理方法，根据访存指令对数据缓存的访问需求控制数据缓存的活动。
In this paper, we propose an on-demand mechanism for data cache leakage power management, which manages data cache activities according to the demand of memory accessing instructions.
本文提出面向访问需求的数据缓存泄漏功耗管理方法，根据访存指令对数据缓存的访问需求控制数据缓存的活动。
In this paper, we propose an on-demand mechanism for data cache leakage power management, which manages data cache activities according to the demand of memory accessing instructions.
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