在单指令流单数据流结构中，有单一的指令周期，在执行前，单个处理机按序取操作数。
In an SISD architecture there is a single instruction cycle; operands are fetched serially into a single processing unit before execution.
cpi值越高，则运行指令所需的周期就越多，这意味着程序的运行性能未达到最优。
A higher CPI value indicates that more cycles were necessary to run the instruction, implying suboptimal execution of the program.
POWER 5芯片有两个硬件指令线程，在每个周期都能够执行多个指令，这可以提高性能。
The POWER5 chip has two hardware instruction threads that are both capable of issuing multiple instructions per cycle, which causes a boost in performance.
它的第一个设计非常简单，所有指令都在一个时钟周期内完成。
Its first design was very simple and all instructions were completed in one clock cycle.
POWER 6处理器有两个能够在每个处理器周期发出多条指令的硬件指令线程，从而改善了性能。
The POWER6 chip has two hardware instruction threads that are both capable of issuing multiple instructions per cycle, which causes a boost in performance.
在这个程序中，完成指令1需要花费4个时钟周期。
In this program, it takes four clock cycles for instruction 1 to finish.
SPU本身使用向量操作，每个时钟周期可以执行多达8条浮点指令。
An SPU USES vector operations itself and can thereby execute up to eight floating point instructions per clock cycle.
从消除信号阻塞到进程执行下一个指令之间，必然会有时钟周期间隙，任何在此时间窗口发生的信号都会丢掉。
There has to be some gap of clock cycles between the unblocking of signals and the next instruction carried by the process, and any occurrence of a signal in this window of time is lost.
不过对于现在来说，我们将简单地展示如何通过调整selb和stqd指令的顺序来节省两个时钟周期。
However, for now, I will simply show how to save two clock cycles by adjusting the order of the selb and STQD instructions. Here is the new order.
同时多线程处理器在每时钟周期从多个线程读取指令执行，极大地提高了指令吞吐率。
Simultaneous Multithreaded Processors improve the instruction throughput by allowing fetching and executing instructions from several running threads simultaneously in each clock cycle.
为进一步降低算法耗费，定义了计算周期的多个层次，最终给出实时参考姿态指令，用以实现参考轨迹的姿态跟踪控制。
To further reduce calculation cost, multiple computing cycles were defined. The output reference attitude command was used to realize the attitude tracking control of reference attitude trajectory.
目前，国内大部分水厂的滤池自动反冲洗控制主要通过滤池工作的时间周期来启动反冲洗指令。
At present, time period of filters are mainly used for starting up the backwashing instruction to control filter backwashing automatically in most of domestic water plants.
这些快速变化的指令输入可以是周期的、随机的以及它们的组合。
Such rapidly varying command inputs (or disturbance) may be periodic, random, or a combination thereof.
举例来说，八月推行的用能产品指令(EuP)建立基于整个产品生命周期环境影响的法规。
For example, the Energy-using Products (EuP) directive, launched in August, creates regulations based on the environmental impact of the entire life cycle of a product.
POWER 4微处理器每个时钟周期收集一组指令(最多有5个)，并在每个时钟周期内完成一组指令。
The POWER4 microprocessor collects a group of up to five instructions per clock cycle and can complete one group of instructions per clock cycle.
这需要修改oprofile的内核代码来周期性地对SPU指令指针进行采样。
This requires changes to the OProfile kernel code to sample the SPU instruction Pointers regularly.
在读操作中，如果发出了这个指令，那么两个时钟周期后，读出数据无效，数据总线进入高阻状态。
During a READ operation, When this command is issued, data outputs are disabled and become high impedance after two clock delay.
文中对陆航数据链轮询组网模式的工作流程和指令优先模式进行了分析，进一步讨论了轮询超时值和轮询周期的设定。
The working process and injunction-first mode of army aviation data link using poll protocol is analyzed, and setting-up of overtime and the cycle time value about poll protocol is discussed.
POWER 5微处理器使此吞吐量增加了一倍，每个时钟周期收集两组指令(每组最多有五个)，并在每个时钟周期内完成两组指令。
The POWER5 microprocessor doubles that throughput by collecting two groups of up to five instructions per clock cycle and completing two groups per clock cycle.
请求周期处理器负责处理请求周期内的指令。
The request cycle processor is responsible for handling instructions during the request cycle. It's used by RequestCycle, which calls its methods in the predefined order.
请求周期会经历若干状态并会根据当前状态向请求周期处理器发出不同的指令。
The request cycle goes through several states and, depending on the current state, sends different instructions to the request cycle processor.
设计一个能够在一个时钟周期执行一条指令的简单指令系统才是更有效的。
It is more efficient to design a simple instruction set that enable the execution of one instruction per clock cycle.
除了处理器时钟速度外，另一个重要的处理器性能度量是每条指令的时钟周期(CPI)。
In addition to processor clock speed, another important processor performance metric is clock cycles per instruction (CPI).
CPI表示一个指令平均占用多少个周期。
CPI means how many cycles an instruction takes to complete in average.
延时——一条指令用来产生最终值所使用的时钟周期数。
Latency — The number of clock cycles an instruction USES to produce a final value.
在第二章中，读者知道了在每个机器周期内处理器取出并执行一条指令。
In Chapter 2, we learned that the processor fetches and executes a single instruction during each machine cycle.
除了那些组件内容和视图相关的钩子外，指令有相同生命周期钩子。
A directive has the same set of lifecycle hooks, minus the hooks that are specific to component content and views.
幸运的是，它们也不是必须的。我们不需要在指令和组件上添加生命周期钩子接口就能获得钩子带来的好处。
Fortunately, they aren't necessary. You don't have to add the lifecycle hook interfaces to directives and components to benefit from the hooks themselves.
流水线是 CPU所使用的一个众所周知的概念，它用于减少取指令-译码-执行 周期中出现的延迟。
Pipelining is a well-known concept employed by CPUs for reducing the latency involved in the fetch-decode-execute cycle.
流水线是 CPU所使用的一个众所周知的概念，它用于减少取指令-译码-执行 周期中出现的延迟。
Pipelining is a well-known concept employed by CPUs for reducing the latency involved in the fetch-decode-execute cycle.
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