此时间间隔的默认值为单个指令周期(10毫秒)。
The default value for this interval is a single clock tick (10 milliseconds).
指令周期是微处理器通过对指令进行处理的过程。
The instruction cycle is the procedure a microprocessor goes through to process an instruction.
但是由于指令周期考虑不全和硬件自身的原因易引起定时误差。
Because instruction period is not completely considered and the hard ware is not perfect, it is easy to cause error.
在单指令流单数据流结构中，有单一的指令周期，在执行前，单个处理机按序取操作数。
In an SISD architecture there is a single instruction cycle; operands are fetched serially into a single processing unit before execution.
在那些日子里，使用电脑意味着编写代码保存一个字节在这里，一个指令周期后又再取出来放到那里。
In those days, working with computers meant writing code to save a byte here and an instruction cycle there.
cpi值越高，则运行指令所需的周期就越多，这意味着程序的运行性能未达到最优。
A higher CPI value indicates that more cycles were necessary to run the instruction, implying suboptimal execution of the program.
从消除信号阻塞到进程执行下一个指令之间，必然会有时钟周期间隙，任何在此时间窗口发生的信号都会丢掉。
There has to be some gap of clock cycles between the unblocking of signals and the next instruction carried by the process, and any occurrence of a signal in this window of time is lost.
您只需要记住提示限制和一个事实：提示指令确实需要占用程序的一个周期。
Just keep in mind the hint restrictions as well as the fact that hint instructions do take up a cycle of your program.
POWER 6处理器有两个能够在每个处理器周期发出多条指令的硬件指令线程，从而改善了性能。
The POWER6 chip has two hardware instruction threads that are both capable of issuing multiple instructions per cycle, which causes a boost in performance.
POWER 5芯片有两个硬件指令线程，在每个周期都能够执行多个指令，这可以提高性能。
The POWER5 chip has two hardware instruction threads that are both capable of issuing multiple instructions per cycle, which causes a boost in performance.
请求周期会经历若干状态并会根据当前状态向请求周期处理器发出不同的指令。
The request cycle goes through several states and, depending on the current state, sends different instructions to the request cycle processor.
POWER 5微处理器使此吞吐量增加了一倍，每个时钟周期收集两组指令(每组最多有五个)，并在每个时钟周期内完成两组指令。
The POWER5 microprocessor doubles that throughput by collecting two groups of up to five instructions per clock cycle and completing two groups per clock cycle.
不过对于现在来说，我们将简单地展示如何通过调整selb和stqd指令的顺序来节省两个时钟周期。
However, for now, I will simply show how to save two clock cycles by adjusting the order of the selb and STQD instructions. Here is the new order.
SPU本身使用向量操作，每个时钟周期可以执行多达8条浮点指令。
An SPU USES vector operations itself and can thereby execute up to eight floating point instructions per clock cycle.
POWER 4微处理器每个时钟周期收集一组指令(最多有5个)，并在每个时钟周期内完成一组指令。
The POWER4 microprocessor collects a group of up to five instructions per clock cycle and can complete one group of instructions per clock cycle.
这需要修改oprofile的内核代码来周期性地对SPU指令指针进行采样。
This requires changes to the OProfile kernel code to sample the SPU instruction Pointers regularly.
要想让分支提示变得非常有效(这样分支就根本不会暂停了)，就必须设置至少4个指令取出组和分支指令之前的11个周期。
For a branch hint to be most effective (so that the branch does not stall at all), it must be set at least four instruction fetch-groups plus 11 cycles before the branch instruction.
请求周期处理器负责处理请求周期内的指令。
The request cycle processor is responsible for handling instructions during the request cycle. It's used by RequestCycle, which calls its methods in the predefined order.
如果这些条件不都满足，或者第二条指令在执行之前需要等待依赖项，那么它们可以在单独的周期中执行。
If these conditions are not all met, or if the second instruction needs to wait for dependencies before issuing, then they are issued in separate cycles.
延时——一条指令用来产生最终值所使用的时钟周期数。
Latency — The number of clock cycles an instruction USES to produce a final value.
除了处理器时钟速度外，另一个重要的处理器性能度量是每条指令的时钟周期(CPI)。
In addition to processor clock speed, another important processor performance metric is clock cycles per instruction (CPI).
流水线是 CPU所使用的一个众所周知的概念，它用于减少取指令-译码-执行 周期中出现的延迟。
Pipelining is a well-known concept employed by CPUs for reducing the latency involved in the fetch-decode-execute cycle.
CPI表示一个指令平均占用多少个周期。
CPI means how many cycles an instruction takes to complete in average.
暂停（Stall） ——处理器不开始执行新指令处的时钟周期。
Stall -- A clock cycle where the processor does not begin a new instruction.
指令4可以在指令3之后紧接的那个时钟周期执行，因为它不需要指令3的结果来执行。
Instruction 4 can be issued in the clock cycle immediately after instruction 3 because it does not require the result of instruction 3 to execute. You can visualize it like this.
换句话说，软件中断常常在指令运行周期的开始发生。
In other words, SOFTWARE interrupts always occur at the beginning of an instruction execution cycle.
幸运的是，它们也不是必须的。我们不需要在指令和组件上添加生命周期钩子接口就能获得钩子带来的好处。
Fortunately, they aren't necessary. You don't have to add the lifecycle hook interfaces to directives and components to benefit from the hooks themselves.
除了那些组件内容和视图相关的钩子外，指令有相同生命周期钩子。
A directive has the same set of lifecycle hooks, minus the hooks that are specific to component content and views.
在每个周期，处理机从多个线程取出多条指令调度执行。
At per cycle, processor fetch many instruction from many thread to manage operation.
在每个周期，处理机从多个线程取出多条指令调度执行。
At per cycle, processor fetch many instruction from many thread to manage operation.
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